1. Field of the Invention
The invention relates to a phase-locked loop, and more particularly to a phase-locked loop reducing power consumption.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit for maintaining phase and frequency of a clock generated by the PLL. The PLL is frequently utilized in a wireless communication system or an optical device. The clock is required when the data signal is decoded. The phase and the frequency of the clock determine whether the data signal is correctly decoded